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DTSTART;TZID=America/Sao_Paulo:20230515T180000
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SUMMARY:Charla de Adrian Cristal:  Chips & supercomputers work at Barcelona Supercomputing Center
DESCRIPTION:Los invitamos a la charla que dará Adrián Cristal\, graduado nuestro trabajando en el Barcelona Supercomputing Center (España)\, haciendo investigación y desarrollo tecnológico en el área de arquitecturas del procesador. \nDía: 1/5/2023\nHora: 18:00hs\nLugar: Sala 1606 \nLa charla de Adrián va a tener dos partes: \nPARTE 1: Chips & supercomputers work at Barcelona Supercomputing Center \nUn poco de historia del BSC\, qué es lo que hacemos\, hacia dónde vamos\, y las oportunidades para desarrollar su carrera allá. \nPARTE 2: Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for Vitruvius+High Performance Computing Applications \nThe maturity level of RISC-V and the availability of domain-specific instruction set extensions\, like vector processing\, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High-Performance Computing (HPC) application domain. In this paper1 \, we present Vitruvius+\, the vector processing acceleration engine which represents the core of vector instruction execution in the HPC challenge that comes within the EuroHPC initiative. It implements the RISC-V vector extension (RVV) 0.7.1 and can be easily connected to a scalar core using the Open Vector Interface (OVI) standard. Vitruvius+ natively supports long vectors: 256 Double Precision (DP) floating-point elements in a single vector register. It is composed of a set of identical vector pipelines (lanes)\, each containing a slice of the Vector Register File (VRF) and functional units (one integer\, one floating-point). The vector instruction execution scheme is hybrid in-order/out-of-order and is supported by register renaming and arithmetic/memory instruction decoupling. On a standalone synthesis\, Vitruvius+ reaches a maximum frequency of 1.4 GHz in typical conditions (TT/0.80V/25°C) using GlobalFoundries 22FDX FD SOI. The silicon implementation has a total area of 1.3 mm2 and maximum estimated power of ∼920 mW for one instance of Vitruvius+ equipped with eight vector lanes.
URL:https://www.dc.uba.ar/event/charla-de-adrian-cristal-chips-supercomputers-work-at-barcelona-supercomputing-center/
LOCATION:Sala 1606
CATEGORIES:Agenda
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